Design Of High-speed VCO And Frequency Divider For Serdes Application

Compared to the parallel transmission of data,serial transmission which relies on its advantages such as high transmission rate,low complexity and low cost,has become the mainstream of data transmission.Serdes system based on serial link technology has become the hardware basis for high-speed transmission of massive information.The Serdes system converts the parallel TTL signal into serial signal and sends it to the receiver.The clock signal from the received serial signal is recovered by the clock and data recovery circuit in the receiver.The voltage-controlled oscillator and the frequency divider by two,which are keys to the stable operation of the entire Serdes system,are circuit modules with the highest operating speed in the clock and data recovery circuit.A wideband voltage-controlled oscillator with a center frequency of 25GHz and a frequency divider that can divide the output frequency of the 25GHz clock signal are designed for the application of the Serdes system.High operating frequency is a main factor for the performance limitation of oscillator and divider,which is a huge challenge for this thesis.Basic concepts including oscillator operation principle,electrical characteristics of passive devices?inductors and varators?and oscillator`s phase noise model are considered.Meanwhile,complementary cross-coupled transistors consisted of NMOS and PMOS transistors used as negative resistance network of the oscillations biased by current source are adopted.In order to reduce the influence of parasitic capacitance of the MOS transistors on the oscillator,the sufficient frequency tuning range of the oscillator and a small tuning sensitivity K_VCOCO can be realized by switched capacitor array which is digitally controlled.To ensure the normal oscillation of oscillators under the influence of non-ideal factors such as temperature,the current source of the oscillator adopts a digitally controlled current array to adjust the output current between 0²mA.The buffer stage of the oscillator adopts a differential amplifier structure,which can amplify the differential clock signal output by oscillator.Meanwhile,the frequency divider based on the current mode logic structure is used to divide clock signal of 25GHz from the oscillator.TSMC 40nm CMOS process is used to implement the circuit design,layout design and post simulation.The oscillator consumes about 9mW under 1.2V supply voltage and outputs the full swing of output oscillation signal about 800mV.The tuning frequency of oscillator ranges from 24.5GHz to 29.8GHz.The phase noise of lower than-90dBc/Hz at 1MHz and the maximum K_VCOCO of about 960MHz/V are obtained.In conclude,the oscillator's post simulation results meet the requirements of the project.The divider's self-oscillation frequency of about 13.25 GHz under 1.2V supply voltage and the minimum half of full input swing required by the divider of80mV are obtained by the post simulation of the frequency divider.Moreover,four phase clocks can be output by the frequency divider.