Sha - 3 Blake Asip Implementation Of The Algorithm

With the development of Mobile Interent, the algorithm of digital signature and password authentication become more and more widely used on embedded systems such as cell phones and Tablet PCs. Being the fundamental of these algorithms, the importance of hash functions are increasing. Unfortunatelt, recently the widely used hash algorithm MD5and SHA-1is seriously threatened. In response to this situation, the NIST launched a competition of SHA-3to find a new hash algorithm replacing SHA-1and SHA-2which is only with minor improvement to SHA-1. The BLAKE algorithm as one of the final-round candidates, though has shown its advantages, still lacks effective and flexible implementations on the embedded systems, as impedes its application.Facing to an efficient approach of the BLAKE algorithm on an embedded system, this paper proposed an application specific instruction-set processor aiming at the BLAKE algorithm. To achieve this target, this paper first constructs a mathematic model according to the characteristic of BLAKE algorithm to evaluate its performance. Then on the basis of other’s work, we suggested a complete set of method to exploring the design space of the BLAKE G-function thus achieve an optimal instruction set specially designed for G-function as well as the structure of relating supporting hardware and input/output pattern, to instruct the hardware design of the processor. Moreover, according to the result of exploring, we design a embedded ASIP and describe it from both hardware and software aspect, thus successfully fulfill the target that implement the BLAKE algorithm on an embedded system.To verify the proposed application specific instruction-set processor, we synthesize it with the Synopsys Design Compiler (DC) under TSMC65nm low power standard CMOS technology. Based on the hardware, the software works realize BLAKE-256as behalf of the32b BLAKE and BLAKE-512as behalf of the64b BLAKE. The proposed ASIP achieves the maximum frequency of1001MHz. The Tp for32b(64b) BLAKE is335(176) Mbps and the corresponding CpB is23.81(45.39). The total area cost of the ASIP is28.48and28.07kGE for CaseA and CaseB respectively. The result of tape-out illustrates that under1.3V voltage, the proposed chip can work at a frequency of890Mhz with134mW, thus reach the performance target-a throughput of300Mbps. So this approach arrives at the predetermined target of an effective ASIP for BLAKE algorithm. Meanwhile, being a processor, the other four SHA-3candidates can also be executed on it. As shown the flexibility of the proposed processor. As conclusion the proposed processor is very suitable for security applications on embedded systems.