Research On Techniques Of Reliability Evaluation Of Application Specific Instruction Set Processor

Such factors as deep-submicron effects, more and more complexity, urgent demand on time-to-market make ASIC (Application Specific Integrated Circuits, ASIC) face great challenge. ASIP (Application Specific Instruction Set Processor, ASIP) has proved its superiority to ASIC in special flexibility, and gets more and more attention in research field. In the methodology of ASIP, attribute evaluation is an indispensable step. It provides statistics for the design of instruction set and the execution techniques in target architecture.On the other hand, with the design goal turning towards low power consumption and high performance, tendency of small-scale circuit design and reduction of supply voltage make more restriction on processor design. This leads to more frequent occurrence of soft error. Soft error is generated by high-energy particles. It can change the memory contents by inverting storage bits, and thus to do harm to processor running. Nowadays, in addition to performance and power consumption, reliability evaluation of storage units has become another important attribute in ASIP design. This dissertation takes deep research on reliability evaluation method of storage unit in ASIP. The main work and contribution are:(1) Make research on reliability evaluation method, and present a novel method that is suitable to ASIP design environment. The character of this method are:It starts the research at instruction behavior, and analyzes the effects made by soft error on storage units in two aspects: instruction set design and execution mechanism design;It divides the evaluation process into two phases. In the first phase, ineffective instructions are explored. In the second phase, statistical information is collected. Being different from traditional methods, the evaluation method presented in this dissertation doesn't take times of structure-level simulation to compute the probability that a soft error can affect the processor running.It can be applied in retargetable ASIP design environment. Nowadays, there has not been a sophisticated reliability evaluation mechanism that can be utilized by ASIP design environment. The method presented in this dissertation overcomes the main difficulties brought by retargetability. It makes full use of processor model and high-level simulator, and analyzes the instruction behavior and operation on units systematically.(2) Make research on the technique of processor modeling and simulator implementation. Evaluation can be seen as a middle stage in the ASIP design. It takes input data from simulator. The evaluation results are used for next time of design space exploration. Therefore, evaluation method has close relationship with many stages in ASIP design environment, including processor model, its formal representation, and simulation on different levels. This dissertation presents a three-level model which models ASIP at instruction level, abstract resource level and discrete event level. The formal representation xpADL takes XML as its meta-language and has great structure character, complete description ability and strong flexibility. It provides integrate formal template for processor model, and offers corresponding mechanism for static information extraction in reliability evaluation, thus to ensure the retargetability of evaluation. Function-level and cycle-accurate simulators are used to analyze the architecture design's effects on reliability of storage units. They are also used to collect dynamic data information in evaluation. Because the performance of high-level simulation is superior to that of structure-level one, this method has better evaluation efficiency.(3) Make research on implementation techniques of evaluation method in ASIP design environment. Every time of design space exploration in ASIP, the candidate architectures are different. This difference should be attained by simulator generator and evaluation mechanism, and it's the most challenging task in retargetable evaluation. Aiming at resolving the problem, this dissertation combines static analysis method and dynamic running method, and completes evaluation in the following three aspects:It makes use of the analysis technique related to architecture description language and injection-fault method based on instruction to analyze the instruction word's effects on reliability of storage units;It uses functional simulator to analyze the instruction operation dependency, thus to study application's effects on reliability of storage units;It uses cycle-accurate simulator to study the execution mechanism and pipeline techniques in candidate architecture, and to collect statistical data information ofevaluation.In addition, the method presented in this dissertation is not restricted to specific architecture, and all the techniques that implement this method can be performed in different kinds of ASIP design environment. Therefore, the reliability evaluation method has wide application perspective.