Instruction Set Design For Encryption Application Specific Instruction Set Processor

Different application imposes significantly different requirements on design and implementation of processor architectures. Specific designed device promises an optimal fit to a particular application. Designing Instruction Set Architecture (ISA) of the Application Specific Instruction set Processor (ASIP) is based on deep understanding of the application algorithm, while understanding of the algorithm depends on analyzing related source code. An instruction set is designed for the SHA encryption application algorithm in this thesis. The SHA source code of the NIST encryption secure hash algorithm is provided by MIBENCH, which is an embedded-benchmark-providing organization from University of Michigan. This thesis was composed of the following three parts:1. Design fine-grained source code profiler used for ASIP design. Traditional source code profiler doesn't provide enough statics information for the ASIP design, A new source code profiler: quantum-profiler is designed to meet these requirements. This profiler is based on the compiler intermediate code which was generated by the LANCE compiler, and is implemented in Python script language. This profiler does not only give the statics of the basic C operations and sub-functions, but also gives the statics of basic block(BB) execution and the number of variables in sub-functions. The statics of BB execution can greatly help the custom CISC instructions design, while the statics of the number of variables can guide the maximum heap and stack size decision.2. Instruction set design for the SHA encryption ASIP. The characteristics of the sha security algorithm source code is extracted, and then an application specific instruction set is designed based on these characteristics, which is achieved by extending the ISA of the OR1K. All custom instructions are implemented as a coprocessor tightly coupled to the base processor.3. Architecture design and hardware implementation for the coprocessor which is mentioned in part 2. To implement the function of these custom instructions, the specific architecture for the processor is designed, including scheduling and the coupling of the coprocessor and base processor. The intermediate registers are also designed to solve the problem caused by multiple operators for the custom instructions. The hardware design is implemented using Xilinx ISE 13.1 tool.Experiment results show that the quantum-profiler presented in this thesis can guide the specific ISA for the ASIP design well, and using the designed instruction set the processor can run the program of sha algorithm with higher performance while hardware cost is slightly increased.The processor, which includes the base processor and the co-processor, is synthesised using the SYNOPSYS Design Compiler. The synthesis result show that the clock frequency is increased to 1.78 times of that of the base processor.