Study On Application Specific Instruction Set Processor For Video Coding And Its VLSI Implementations

With the increasing performance requirement of video coding, the design of ASIP (Application Specific Instruction-set Processor) for video coding has been a research hotspot both in academy and industry. This paper focuses on following three aspects:1) Design of a programmable bitstream processor for multiple video coding standardsThis paper proposes an efficient bitstream parser for bitstream parsing and VLD (variable length decoding) in video decoding. The proposed design presents an extension instruction set to accelerate some kernel functions of bitstream parsing, such as showbits, getbits, flushbits and so on. With the LNZ group algorithm, the proposed bitsteam parser can meet the performance requirements of H.264 real time decoding at 1280i resolution at 30 frames per second within 150MHz. The synthesis result shows that the hardware cost is about 7K gates of logic and 2K byte RAM under a 0.18um COMS technology. Furthermore, it is applied to the VLX specific function unit of Spock, which is an embedded RISC core developed by us.2) Design of a parallel memory architecture for video codingIn order to efficiently exploit the performance of SIMD architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed in this paper. Based on the analysis of required access formats for video coding, we present two novel skewing schemes. A-scheme provides conflict free access to adjacent elements (8-bit and 16-bit data types), and S-scheme supports parallel access with power-of-two intervals both in horizontal and vertical directions. The simulation result shows that the proposed design achieves 1.28×speedups in H.264 real time decoding, compared to the byte-addressable memory architecture. Furthermore, the hardware implementation is simple and scalable for different data bus widths. As the number of memory modules increasing, the advantage is more and more evident.3) Design of a video processor-SchubertThe EDO-SIMD instruction set architecture (ISA) is proposed to to reduce the data conversion and rearrangement overhead for bringing data in a form amenable to SIMD processing. It can provide flexible formats of operands by the additional data permutation network between the register file and SIMD computing units. We develop a dual-pipeline video processor - Schubert to support EDO-SIMD ISA. The architecture of Schubert is based on decoupled access and execution concept. The execution pipeline is for EDO-SIMD processing, and the access pipeline is for the vector load/store unit. Further, a specific instruction set extension is proposed for video coding on Schubert platform. The simulation results show that H.264 decoding at QCIF and CIF resolution at 30 frames per second is achieved within 11.4MHz and 49.1MHz respectively of Schubert performance.