Research On Instruction Set And Design Of Data Path For Application Specific Video Processor

The Application Specific Instruction set Processor (ASIP), which features the high efficiency of Application Specific Intergrated Circuits(ASIC) and the flexibility of General Purpose Processor (GPP), has and will have been popular in video processing domain. To enhance the performance of the ASIP for video processing, we do some valuable research on both of instruction set design and architecture implementation aspects.Through study and analysis on the MediabenchⅡVideo&Image benchmarking suite, the characteristics of video application were summarized, which were found high proportion of parallelism, full of combined instruction operation, and typically using small integer data types. So a SIMD and VLIW mixed instruction set architecture(ISA) is proposed. The ISA combines useful features of SIMD and VLIW architecture, supports conditional execution, saturation arithmetic and explicit data organization, includes some video application specific instructions to boost video processing. Some video processing kernels' simulation results show that, compared to MMX and SSE2, the SIMD and VLIW mixed ISA can achieve better performance in video processing.VLIW architecture may result in code size expansion because of lacking of instruction-level parallelism. To solve it, this dissertation proposes a new encoding method, dynamic variable-length encoding. The dynamic variable-length encoding discards the NOP instruction from the VLIW instruction bundle, and uses 32bit and 64bit, two types of instruction-width. Experimental results show that, compared to traditional VLIW defined-length encoding, the dynamic variable-length encoding can reduce code size to 20%～35%. In order to support the dynamic variable-length encoding and special instruction format, the implementation of the mixed ISA's assembler is presented in this dissertation. The assembler is organized as a two-pass structure to ease the forward reference.After lexcial analysis, syntax analysis and code generating process, the assembler will produce machine code and instruction fetch-control code.The micro-architecture design of the data path module of the video processor is also proposed in this dissertation. The data path module is designed as a 4-way and 4-stage pipeline architecture, including 27 function units such as ALU, multiplier, shifter, etc, supports 1 -way, 2-way, 4-way and 8-way parallel computation and video application specific instructions. Besides, the data path can support operands bypass, states flag generating and results saturated.