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Hardware Implementation Of Configured SHA-2Series Algorithm And SHA-3(BLAKE-32) Algorithm

Posted on:2013-04-21Degree:MasterType:Thesis
Country:ChinaCandidate:X DongFull Text:PDF
GTID:2248330392958210Subject:IC Engineering
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In recent years, with the popularity and widespread using of the Internet, whetheronline shopping, online bank, send and receive e-mail, or in other sensitive to securityrequirements of digital communication field, encryption technology has become animportant tool to ensure data transmission privacy. For such problems, the U.S. NationalInstitute of Standards and Technology (NIST) and the United States Security Agency (NSA)have announced the SHA-1, SHA-224, SHA-256, SHA-384and SHA-512algorithm, andthe SHA-3series algorithm is publicly selected. But, because of the rapid development ofdigital communication, the demand of hash algorithm is getting higher and higher. And thesame system may have different security requirements. So, the software implementation ofSHA hash algorithm can no longer meet the needs of the application at present. Therefore,the hardware implementation of the hash function series has become the focus of ourresearch.This paper firstly analyzes and describes the principle of SHA-2family of algorithmsand BLAKE series of algorithms, and compares some of the work of the predecessors. Inthis paper, a VLSI architecture for the SHA-2family is proposed, in order to meet differentsecurity selection this architecture can flexibility to choose any algorithm in the SHA-2algorithm. In addition, the core part of the hardware structure has been optimized by thefolded structure, with this structure the working frequency is improved and the area isreduced. And a [4G] hardware structure of BLAKE-32algorithm is proposed for high speedand area-limited environment.This paper uses Verilog hardware description language to complete the RTL of theconfigured SHA-2and BLAKE-32hardware circuit design, and uses EDA tools for a logicfunction simulation and verification, and selects the Xilinx FPGA device platform to realizethe and comprehensive. The analysis results show that, the area of two designs are smaller,but the maximum working frequency can reach92Mhz and112Mhz respectively. It issatisfied to the design requirements of the reservation.
Keywords/Search Tags:Hash function, SHA-2, SHA-3, BLAKE-32, Hardwareimplementation, folded structure
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