Research On Technology Of Application Specific Instruction And Reconfigurable Unit Of Elliptic Curve Cryptography Coprocessor Design

The requirement of the flexible and effective implementation of the Elliptic Curve Cryptography (ECC) has become more and more exigent since its dominant postion in the public-key cryptography application. Based on the analysis of the ECC algorithms operation characterism, basic structure features of the ECC application protocols, and the storage characterism, combining vector approach, aiming at designing an application specific vector coprocessor for various ECC algorithms, the design method of the application specific instruction set and reconfigurable cipher process unit is researched in this thesis.Based on the basic operation structure features of the ECC algorithms and the character of the data parallel processing, an instruction set for ECC is proposed following the principle of the ASIP design in the thesis. According to the requirement of the instruction operation, seven basic instructions, including vector modular addition, modular subtraction, modular reduction, modular multiplication, modular square, modular inversion and K-data comparison, have been accomplished. It could support flexible implementation of ECC.Reconfigurable cipher units are designed corresponding to the arithmetic instructions in the thesis. Based on the character of the vector processing and the proper arithmetic algorithm, modular addition and subtraction, modular multiplication, modular inversion reconfigurable cipher processing units are presented in the paper. Each unit is based on a unified architecture with capable of handling arbitrary elliptic curves of the length range from 160 to 576-bit in dual-field. The synthesis and simulation verification for them have been performed based on FPGA and ASIC. It could support effective implementation of application specific instruction.Software simulation, hardware simulation and FPGA verification of the coprocessor design are accomplished on the platform. The work is synthesized by Design Compiler on 0.18μm CMOS standard cell library. Its performance is also compared with other hardware/software implementation. The result shows this design has advantage in high performance and wide flexibility and has high practicality and wide application in the future.