Design And Implementation Of Specific Instruction Microprocessor Based On RISC-? Isa

Matrix operation,as the most popular operation in Advanced Signal Processing,has a wide range of applications in various fields.Among them,matrix inversion has problems such as high computational complexity,large amount of data,and difficult hardware implementation.At present,matrix inversion is widely used in the field of speech signal processing,image processing and machine learning,etc.In order to achieve fast and efficient matrix inversion,the applications of traditional general-purpose processors can no longer meet the requirements under the constraints of constant performance per watt.With the continuous improvement of chip integration,application-specific instruction-set processor(ASIP)that adjusts the processor structure to adapt to specific algorithms has gradually become a hot research topic.In this paper,aiming at the problem of high complexity and slow operation speed of matrix inversion,a specific instruction processor for matrix inversion based on RISC-? ISA is proposed.The main work content is as follows:(1)Firstly,research,analysis and derivation proved the basic principle of matrix operation by vector operation,briefly analyze the commonly used matrix inversion,select the Sherman-Morrison formula as the basic inversion algorithm,and combine the specific instructions to decompose the Sherman-Morrison formula,reduce the total number of steps of the the algorithm from 4n3+n2 to 4n2+n,and explore the basic method of implementing specific instructions in tinyriscv processor,which provides theoretical support for further expanding the instruction accelerator in the processor.(2)Comparing the two acceleration structures of the extended V-ALU and the extended vector coprocessor,and choose the extended V-ALU structure with less hardware resources occupation,high acceleration ratio,and strong applicability.Besides,design based on 4th,8th and 16th order V-ALU structure to realize the inversion of different order matrices.Under this acceleration structure,parallel arithmetic units are designed for addition and subtraction operation instructions and multiplication operation instructions respectively according to the operation type,and the storage structure of the tinyriscv processor is optimized to improve the operation speed.(3)The overall design of the specific instruction microprocessor is realized based on the extended V-ALU acceleration structure and specific instruction optimization method,including specific instruction encoding,vector operation unit and floating-point operation.Moreover,the method of reducing the weight of the bit of the division operation result is adopted to reserve the decimal place to solve the error problem caused by the cyclic operation process.(4)Building a software and hardware test platform to test the specific instruction microprocessor.The test results show that after using the vector specific instruction accelerator,the number of inversion calculation cycles of the 4th,8th,and 16th matrices are reduced to 63%,85.6%and 92.6%of those without specific instructions,and the error of the calculation results can be reduced to 10-3 the following.Finally,the ASIC design of the processor is realized based on the 180nm CMOS process.