Design And Impletation Of Task Compiler For REMUS-II Coarse-Grained Reconfigurable Processor

With the development of IC industry, the demands for efficient flexiblecomputing systems are increasing. Reconfigurable processor combines theflexibility of general purpose processor and high performance of ASIC. Thetypical structure of reconfigurable processor is a main controller coupledwith a reconfigurable unit. The task compiler of reconfigurable processorcompiles the application program to configuration code, becoming a vitalelement of reconfigurable system.This paper proposes a task compiler LOOPCC for REMUS-IIcoarse-grained reconfigurable processor. The frontend of the compilerconverts the parallel instruction code to data flow graph(DFG).Thebackend of the compiler divides the DFG into several sub-graphs and mapsthem onto the reconfigurable array, then generates the configurationcontexts and supportive codes for the main controller. In order to removethe redundant information and generate a smaller DFG, LOOPCC utilizespartially loop-unrolling technique in its frontend part. In order to make fulluse of the hardware resources in REMUS-II system and make theprocessor more efficient, the backend part of LOOPCC introduces variousoptimization methods. Constant input abstraction diminishes the amount ofDFG inputs. Context reusing and internal data flow optimization enablethe computing array to compute more than once after a certain arrayreconfiguration.Experiments are conducted to verify the LOOPCC compilation flowand analyze the performance. The LOOPCC mechanism reduces theconfiguration context amount and compilation time but enhances the REMUS-II performance. The experimental results show that LOOPCCreduces compilation time by28%and configuration contexts amount by80%and achieves a3times speedup to the REMUS-II performancecomparing to the previous compiling method.