Research On Compiler Of Coarse-grain Reconfigurable Array Processor

In recent years, coarse-grained reconfigurable architectures have become increasingly important alternatives for accelerating compute-intensive applications. More and more coarse-grained reconfigurable architectures have been proposed. Coarse-grained reconfigurable architectures become important due to its combination of the advantages of both ASICs and general processors. However, the problem how to mapping applications automatically and efficiently onto processing elements is still to be resolved. Undoubtedly, if all applications are mapped on hardware manually, the workload of application will greatly increase and resoures utilization rate will probably lower.According to these problems, this paper finds out methods to map programs on the loop based coarse-grained reconfigurable architecture, then a compiler of LEAP(Loop Engine on Array Processor), which realize that mapping loops on reconfigurable array automatically, is designed and implemented.LEAP Compiler implements the"Based on Intermediate Format"design scheme, which can get program information through analyzing the intermediate format of object program but not its source code. In order to gain the loops information in the source program, this paper introduces the general approach to automatically distinguish loops from the LANCE intermediate representation of the program and analyse loops structure characteristic, and has implemented the two functional modules.Aimed at reconfigurable array structure of LEAP and instruction structure, the method of logicly mapping loops on LEAP is proposed and logical mapping tool for LEAP processor has been implemented. Regarding flow dependence, anti-dependence, input dependence and flow dependence within iteration, this article proposes these methods which solve these data dependence when logical mapping on array architecture, and the methods have been integrated reasonably when realized the logical mapping tool. So the problem of data dependence has been solved effectively.In order to implement physically mapping of data flow graph on LEAP, the methods of simultaneous layout and wiring, optimize layout with the simulation annealing algorithm and the multi-configuration binary files producer has been proposed, and the physical mapping tool has been implemented with these methods.To demonstrate the effectiveness and superiority of LEAP Compiler, this paper selects some typical loops of scientific computing and media processing,and then map these loops on the LEAP architecture by LEAP Compiler and the manual way separately, and do the contrastive analysis to the two mapping results. Outcome of the test shows that the LEAP Compiler works correctly. And it is designed logically and implemented effectively.