Design Of Dynamic Data Scheduling Modeland Part On The Reconfigurable Computing System Chip

The applications require the computing instruments which have higher performance and flexibility. The reconfigurable computing systems are produced under the applications' requirement and the development on the hardware technology. It possesses the high performance of ASICs and the high flexibility of GPPs. The researchers focus on how the reconfigurable computing systems settle the applications, especially the dynamic applications. In the thesis, the main topic is about how the dynamic applications are mapped on the reconfigurable computing system, including the following aspects:1. The dynamic applications are described through the control data flow graph. There are some branching vertices that represent operations that evaluate conditional clauses. The dynamic applications can be represented completely through this figure.2. According to the characteristics of conditional branch and iterative branch, two approaches are proposed to solve the branch prediction, one is considering the global branch prediction and branch time to predict conditional branch, and the other is used to predict the iterative branch through dynamic list. This combination of two approaches and the operation autonomy on Morphosys-M2 structure are used to solve the conditional branch and iterative branch, the result shows that the whole time is shortened.3. In order to solve the allocation of the reconfigurable cells and the data, the formula is explored. It can give the rational allocation in a variety of operating modes which makes the system run more efficiently.4. The thesis designs and implements the frequency divider and floating-point operation during cluster scheduling for dynamic applications based on VHDL. Because the counter is used and controlled by the complete waveform, the controllable arbitrary integer frequency divider is designed and used for the dynamic cluster scheduling. At the same time, in order to overcome the defect caused by converting the fixed-point into floating-point operation, a fast single-precision floating-point arithmetic unit, which is designed, will greatly reduce the burden of compiling system and improve the efficiency of operations.