Design For Test And Formal Verification Of Video Format Convert Chip

The testing of IC is the primary way to improve the production quality and tosave the cost. With the development of the complexity and integration of IC, thetesting of IC becomes more and more difficult, therefore, the importance of testingbas been recognized gradually.The design for test is the methology developed rapidly to resolve the testingproblem.Its main theme is to add extra circuit to make the testing easier, with theconsideration of test coverage. Also, to make sure that, the insertion of test circuitshould make no affection to the original circuit, a formal verification must be excuted.This item makes the research to methology of design for test, and designs thetesting circuit of Video Format Converter chip.The design for test of VFC whichconsists of internal logic and embeded memory, has been designed by bottom to topflow.Internal logic and registers are designed under scan chain design methology,which means that internal registers are switched by scan cells and form a scan chain.This makes the internal nodes controllable and observable by setting the registervalues, data shifting and capturing, as well as adding extra decompressor andcompactor at the edge of core logic to make the test patterns compressed, whichreduces the mount of the test patterns.The testing of embed memory is designed as aBIST circuit. Based on the March23N algorithms, presented to resolve the problem offault coverage, BIST controller and response comparetor are designed to generatorstimulus and analyze response. The crucial design of this part is to set up thealgorithms. March23N algorithms is advanced to cover all faults including specificfaults which can’t be covered by traditional algorithms.In the top, a whole testingsystem is established by adding boundary scan circuits to connect internal scan chainand embed BIST circuits, and setting user defined instruction and registers.The results of simulation indicate that, the presented scan tesing system is able toachieve a98.28%test coverage and the function of BIST controller is accordant to theMarch23N algorithms, also, the BIST circuit can detect the specific faults that can’tbe detected by traditional algorithms.Formal verification is also excuted to ensure the equivalence between originalcircuit and scan chain inserted circuit, which is reflected in the verification result.