The Implementation Of DFT For A Multi-core System-on-Chip

As the size of integrated circuit technology continues to shrink,the scale of chip integration continues to expand,and the design technology of multi-core SoCs is rapidly developing.The development of integrated circuit technology to deep sub-micron and nano-scale,and the continuous improvement of multi-core CPU architectures,has increased the number of multi-core SoC internal digital logic and the number of IP cores integrated on it,which not only puts more emphasis on the design of multi-core SoCs but also brought enormous challenges to the testing of multi-core SoCs.As a design methodology that has been continuously developed to solve these test problems,testability design has received increasing attention from the industry.The purpose of DFT is to consider the test problem by adding additional test circuits which will not affect the normal function to achieve the testability of the chip in the process of chip design.This article is to develop a complete testability design scheme for the DSDP16 chip developed by the project team and verify its feasibility.The DSDP16 chip is a high-performance chip that integrates two processor cores.It runs fast and has a large number of memories.Numerous IP cores such as CAN,UART,and A429 are used in the design process,making the chip structure more complex and making the test of this chip more difficult.In order to achieve the test goal of the chip and improve its testability,this paper has conducted research and design from the following aspects:(1)The digital function logic inside the chip adopts at-speed scanning path design,which solves the test problems of timing-related transition faults and path delay faults in SoCs with feature sizes below 130 nm.Including the use of on-chip clock controller circuit to generate high-frequency clock of which the at-speed test required.For the problem that the test pattern of the multi-core CPU is too large,the compression design of the scan chain is used.Finally,for the coverage report after the ATPG,the analysis and solution for undetectable faults in the scan design are given.(2)For a large number of embedded memories inside the chip,a bottom-up hierarchical design method is adopted.According to the size and the module,those memories are divided into different groups.Parallel testing is performed within the group and serial testing is performed within the components in the group,which effectively reduces the power consumption of MBIST.(3)For the testing of I/O pins,a boundary scan design was implemented for the DSDP16 according to the IEEE std 1149.1 standard.Through the JTAG interface,the test of the chip's peripheral pin and board-level chip interconnection and the control of the MBIST circuit are completed.Finally,according to the DFT plan that has been made,the specific logic design inside the chip is completed,and the feasibility and effectiveness of these design are verified.