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Based On The 0.18 Mu Mcmos Process 12-100 - Bit Installed Base Design Of Pipeline Adc

Posted on:2013-10-04Degree:MasterType:Thesis
Country:ChinaCandidate:B J ChenFull Text:PDF
GTID:2248330374486381Subject:Microelectronics and solid-state electronics
Abstract/Summary:PDF Full Text Request
Based on the demand for design methods and applications of high speed high accuracy ADC in wireless communication systems, a second-order power optimization method is proposed and applied to the design of a12-bit100-MS/s pipelined ADC.Firstly, several typical architectures of ADC and the key indicators are introduced, and compared. Then the pipelined ADC is chosen to achieve the high speed high accuracy performance, according to their inherent features, different application fields, and the process.Secondly, the first-order power model of pipelined ADC is too coarse to meet the design requirements of high-speed high-precision complex system. A second-order power optimization method is used in the design of pipelined ADC, with detailed analysis of the influences of some non-ideal factors such as switches’nonlinearity, capacitors’mismatch on the working process of pipelined ADC. The computed result shows the possibility of the12-bit100-MS/s ADC using the process. According to the second-order model, the architecture of pipelined ADC is determined, and the power is reduced almost40%.Thirdly, derive the quantitative relationships between ADC indicators and irrational factors, such as switch on-resistance, thermal noises, and the nonlinear amplifiers. Then designed and optimized several key cell circuits encluding the S/H, MDACs, and comparators, according to the second-order minimum settling time of the operational amplifiers.Finally, based on0.18μm1.8V standard CMOS mixed-signal process, the S/H, MDAC, comparators and the whole ADC system are designed and simulated. Given an input of1.6Vpp and49.9MHz, the SFDR, SNDR and the ENOB achieve78dB,70.1dB and11.4separately with a100MHz sampling clock.The simulation results show the effectiveness and practicability of the second order power modeling and optimization method, and the theory of indicator allocation, and provide some reference worth on the design of high speed high accuracy ADC.
Keywords/Search Tags:pipelined ADC, power optimization, parameters’ allocation, second-orderamplifier settling modeling
PDF Full Text Request
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