Systematic Modeling And Configuration Design For Pipeline ADC

ADC(Analog-to-Digital Converter), as the interface between the outside and the inside of the electronic system, needs continuous improvements on integration and complexity with the increasing requirement on its resolution and speed. In the case of continuing reduction of device dimension and lowering of power supply voltage, how to lower ADC's power dissipation without decreasing ADC's performance and how to diminish the negative influence on the data conversion by every non-ideal factor, become a main topic throughout the ADC design. As a prevailing structure in the field of high-speed high-resolution ADC, pipeline ADC has a desire on the problem such as power lowering and non-ideal factor eliminating in the systematic design phase, which could be a key part through the design of the system. Based on the above theory, this paper works on the following topics: reviewing every non-ideal effect for a high-speed high-resolution pipeline ADC, analyzing and quantizing the influence on ADC performance by the non-ideal effects and giving some corresponding improvement methods; utilizing power dissipation and system signal-to-noise ratio as the important consideration parameter, and fixing the systematic architecture for a 14bit high-performance pipeline ADC by careful analysis and comparison.This paper firstly analyzes the factors of SHA (Sample and Hold Amplifier) and MDAC (Multiplier DAC) from system level which have a significant influence for the following circuit design, completing the target separation for the whole ADC. According to the switched-capacitor circuit character in the sampling phase and the operational amplifier settling performance in the holding phase, the main referred design indexes of SHA could be obtained; the parameter requirement for the operational amplifier in MDAC could be deduced from studying MDAC's settling curve, including stable settling error and dynamic transforming time. Secondly, as power dissipation and noise restriction as the clue point, the optimization of ADC architecture could be realized. Giving the principles on stages, the resolution of a stage and the first stage resolution which is used to decide the architecture of the pipeline ADC, the most optimum ADC architecture could be selected from numerous combinations. In the precondition of achieving the requirement of noise, the value of sampling capacitor in every stage of the ADC could be settled in order to satisfying the assumption for the load capacitance and power dissipation. In the end, a design example about configuration optimization, is implemented on a 14bit, 100MSample/s pipeline ADC.This paper is realized mainly with the assistant of the math model description and MATLAB tools. In the analysis of the non-ideal effects, the SIMULINK tool is employed to finish the modeling, and through the course, the influence on the spectrum of output signal by all kinds of effects could be utilized to estimate their extension on the attenuation of ADC performance. In the aspect of configuration selection, the equations deduced from every configuration combination could be modeled by MATLAB programming language. According to simulation and verification for the above model, the main conclusions could be obtained as follows: more stages, relatively less power lost; when the resolution of first stage is higher, the required sampling capacitor is smaller and the power lost could be reduced; obtaining a relative optimization on power dissipation with a scaling-down factor of 1/2; the reduction of power dissipation is based on the theory that in the presupposition of noise restriction, the reducing magnitude of following stages is larger than the increasing magnitude of the first stage power dissipation.