Research And Realization On Systematic Power Optimization Of Pipelined ADC

Due to the comprehensive advantages in speed, resolution, area and power consumption, pipelined Analog-to-Digital converters (ADC) are widely adopted for A/D conversion in high speed, medium-to-high resolution applications especially in rapid growing portable electronic products, which have large demand for them and put forward higher requirements for research on their low power design.On demands for low power applications mentioned, this thesis studies and analyzes the total system power consumption of pipelined Analog-to-Digital converters (ADC) based on major power consumption sources analysis. Through deeply discussing and analyzing the system architecture, working principles and circuit implementation of basic blocks, power consumption modeling was put forward for the key power consumption sources including MDAC (Multiplying DAC) and SubADC. Meanwhile, the factors affecting the power optimization such as the thermal noise limitation, the front-end sampling and hold circuit, the accuracy of the residue amplifiers as well as the optimization of stage unit capacitances were discussed in details. And finally, the thesis derived the system power consumption function with respect to structure parameters including the stage resolution distribution, the scaling down factor of capacitances and specification parameters like the overall resolution and the clock frequency. Based on it, the power optimization problem was abstracted to a math problem of obtainning the optimum values of a multivariate function. Furthermore, by employing a hybrid search algorithm which combines exhaustive search algorithm with genetic algorithm, a CAD tool was developed in MATLAB to solve the optimum structure parameters.Lastly, the power optimization results of different pipelined ADCs with different specifications are derived and compared with each other, which could be utilized to guide system design practice. According to the optimized structure parameters, the key blocks of a 14-bit 100MS/s pipelined ADC were designed in SMIC 0.13μm technology using Cadence software. Simulation results show that the estimated total power consumption is about 180mW, which verifies the effectiveness of the proposed optimization method.