System Design And Modeling For12bit Pipelined ADC Based On The Optimization Of Power And Noise

With the development of video equipment, it had required more and higherabilities of video ADC, and ADC is the core of video ADC. Pipelined structure isoften used in the ADC of video ADC as pipelined ADC can achieve a goodcompromise between speed, accuracy, and power consumption performance. Withthe continuous improvement of the performance of the pipelined ADC, thecomplexity of circuit is also increasing. As system-level design and modeling canshorten the design cycle, increasing design reliability, it has gradually become anessential step in analog integrated circuit design. How to optimize powerconsumption，noise, and other non-ideal factors of pipelined ADC reasonably insystem-level design and modeling, and thus provide theoretical guidance for circuitdesign is the key to the current system-level design of complex analog integratedcircuits.This thesis firstly gives a brief description of12-bit pipelined ADCapplication background the video ADC and its main working principle, todetermine the basic performance indicators of the modeling pipelined ADC. Andthen the the main structure and working principle of the key modules were analysed,such as sample-and-hold circuits, MDAC circuit, Sub-ADC circuits and digitaldelay correction circuit. Based on these analyzes, the sample-and-hold modulestructure was initially identified. Then non-ideal factors of12-bit pipelined ADC(such as noise, power consumption, offset and distortion) was analysed. Twopreferred system architecture of project one (2.5+1.5×7+3) and project four (3.5+1.5×6+3) was choosed based on non-ideality factor, power consumption andchip area compromise. Finally, the ideal model and the non-ideal factors of12-bitpipelined ADC key modules was system-level designed and modeled, respectively.And the advantages and disadvantages of both the preferred architecture for thesystem simulation were compared. Ultimately, the sample-and-hold module wasdesigned and simulated based on the determined design specifications fromsystem-level design and modeling. In this paper, simulink tools was used forsystem-level design and modeling of12-bit pipelined ADC. Simulation resultsshow that the SNR，SFDR and ENOB of project one can achieve63.24dB,80.01dBand10.196bit, respectively. The SNR，SFDR and ENOB of project four can achieve 63.74dB,81.26dB and10.213bit, respectively. The DNL and INL of two peojectsare all between-0.15~0.2LSB and-0.3~0.2LSB, respectively.