Using Nanoscale Technology Research And Design Of Low Power Consumption Adc

The continued scaling of CMOS process has provided greater integration levels ina single silicon chip. Owing to the scaling of MOS transistor and accompanyingreduction of supply, the active area and power consumption can been minishedeffectively. Shorter channel length is offering MOS transistor with higher-frequencycapabilities but lower intrinsic gain, which makes analog circuit design much tougher.Thanks to the absence of linearly gain stage, successive-approximation registeranalog-to-digital converter (SAR ADC) is adaptive in modern process. Beside ofconventional moderate-high resolution and low-speed application, SAR ADC designedfor high-speed, high-resolution and ultra-low power applications has surged in recentyears. SAR structure has been used widely in some ultra-low power applications, suchas wireless sensor, biochemical IC and remote data acquisition system.This dissertation focuses on the design of ultra-low-power SAR ADC as a keycomponent within wireless sensor or biochemical IC system, which is capable ofdigitizing analog signals with varying dynamic range and bandwidth. The leakagecurrent of MOS transistor becomes significant when working in slow clock, and it getsworse in low supply and modern process. To fulfill the demand and solve the exisitingissues, a0.5V-supply ultra-low-power SAR ADC is proposed with reconfigurableresolution (10-bit/8-bit/6-bit) and up-to100KS/s sampling rate. The presented SARADC employs “split-array” structure of DAC and a newly proposed switching method.Based on the delicately designed behavioral model of this proposed SAR ADC, somenonideal effects caused by parasite capacitors and capacitor mismatch have beenanalysed in detail. This design has been validated by the test results of ADC prototype,showing comparable performance in terms of figure-of-merit (89.4fJ/conversion-step)to other excellent works in recent top publications.