Designs Of Low Voltage, Low Power And High Resolution Successive Approximation Register Adcs

Energy-constrained applications such as mobile devices, portable diagnosing equipments, wireless sensor networks, etc., demand energy-efficient ADCs for long life-time of the devices. Meanwhile, the continuous down-scaling of digital supply voltage requires low voltage ADC for SoC integration. In these applications, successive approximation register (SAR) ADC is normally a dominant architecture due to its low power and good reliability under ultra low voltage.First of all, this thesis analyzes and designs a0.5V resolution and sampling rate scalable SAR ADC. An improved clock boosting technique and a level shifter are proposed, which reduces the leakage of sampling switch and resolution-scaling switch significantly as compared to conventional techniques. This has ensured the ADC operating at a wide range of sampling rates and scalable resolutions almost without ENOB degradation. Meanwhile, the linearity of merged capacitor switching (MCS) DAC and the nonlinearity caused by the segmented DAC are discussed. Fabricated in a0.13um CMOS process, the demonstrated ADC achieves ENOB of8.52b,7.42b, and5.97b at10b,8b, and6b modes, respectively. At10bit125kS/s, the entire ADC consumes only3.4μW from a0.5V supply and acquires an FOM of74.6fJ/step.Secondly, this thesis discusses the design of another0.5V12bit SAR ADC with focus on the consideration of the self calibration at low voltage. With aids of the proposed behavior model, relationships among noise of comparators, resolution of calibration DAC, and overall ADC performance are studied. Besides, the challenges at the circuit level for the low voltage self-calibrated ADC are discussed and corresponding solutions are also proposed. Circuit simulation shows the ADC achieves an ENOB of11.1b and a SFDR of79dB with capacitor mismatch up to3%. At12b1MS/s, the ADC exhibits an FOM of12.6fJ/step under0.5V supply voltage.