Design of low-voltage low-power sigma-delta modulators for broadband high-resolution A/D conversion

For several decades, MOS technology has scaled according to "Moore's law," and it is expected that this scaling will continue for at least another decade. As a consequence of the scaling of CMOS technology, digital circuits will continue to benefit from the projected advances in technology. It is not clear, however, that analog circuits will benefit from further technology scaling. Device scaling lowers the supply voltage, thereby leaving less headroom for design. Also, a lowered supply voltage means reduced dynamic range unless the noise floor is reduced, which typically requires increased analog power dissipation. In particular, A/D converters based on sigma-delta (SigmaDelta) modulation are directly subject to the difficulties imposed by the continued scaling of CMOS technology.; The main objective of this research is to identify means of building broadband SigmaDelta modulators in scaled CMOS technologies that will operate at low supply voltages while minimizing power dissipation. After addressing how the scaling of CMOS technology affects the performance of analog circuits, this dissertation introduces a SigmaDelta modulator architecture called a reduced-integrator-swing-range (RISR) SigmaDelta modulator. In addition to enabling operation from a low supply voltage, the RISR SigmaDelta modulator relaxes the requirements on analog circuits, which in turn provides a significant saving in power compared to conventional SigmaDelta modulator architectures.; To develop an RISR SigmaDelta modulator architecture that achieves the targeted performance objectives (15-bit resolution over a 1.25-MHz signal bandwidth) with minimum analog power dissipation, a power minimization process called noise-and-settling constrained power minimization (NSCPM) is developed. From the results of the NSCPM procedure, the final architecture is selected as a 2-2 cascaded multi-bit modulator. Key circuits that enable low-voltage implementation of the proposed architecture are also described.; An experimental implementation of the proposed modulator has been integrated in a 0.25-mum CMOS technology. Operating from a 1.2-V supply, it achieves a dynamic range of 96 dB and a peak SNDR of 89 dB for a signal bandwidth of 1.25 MHz, with analog and digital power dissipation of 44 mW and 43 mW, respectively.