Serdes Level Validation System Level Design And Behavior

In recent years, the development of integrated circuit has characterizes of higher speed and higher degree of integration. In the face of large number of data being deal with, high data transmission has become the new bottleneck instead of operation ability. As a typical technology of serial transmission link, SerDes has been developed quickly. In order to fit for the higher transmission rate and shorter study period, new design methods are created continually combined with new structures and new design tools.After years of development, there exists a quick and efficient flow for design of digital integrated circuit ranging from logic design to physical design and verification. Because of hard work and long period of study, analog and mixed integrated circuit design blocks the efficiency of the whole flow. As a result, system level design combined with behavior level verification has been considered more and more. System level design helps designers consider circuit targets well while behavior model accelerates the speed of verification and improves the efficiency of design.In this thesis, a scheme of SerDes based on the structure of8B/10B is advanced. And then, system level design and behavior level verification of which are discussed, especially for the core models such as PLL, CDR, Serializer and Deserializer.Firstly, the open and close transfer functions of charge pump phase-locked loop in locked state are obtained through approximate linear analyze. Begining with loop bandwidth and phase margin, a flow of system level design is built for making sure the parameters which can affect the performance of PLL. Subsequently, behavior level verification platform of PLL based on behavior model described by Verilog-A is made. Then, system level design and behavior level verification of PLL in SerDes described in this thesis are finished. Besides, by using the behavior model of PLL, the method of choice for loop bandwidth and phase margin is studied and some conclusions are given.Secondly, system level design and behavior level verification of full speed and dual loop CDR based on PLL in SerDes described in this thesis are finished by using the same method.Finally, behavior models of serializer and deserializer based on the structure of shift register are finished by using eye diagram for timing estimate. Combined with generator and detector of PRBS, the whole behavior level verification platform of SerDes is built. After that, transmitter, receiver and self-test mode of SerDes are verified respectively to make sure if the scheme of SerDes advanced in this thesis is viable.