| With the great increase in the scale and complexity of integrated circuit, it is askinga great deal for verification. But the verification technology is much slower than it ofdesign, there is still a huge gap between them, and the work of verification has becomea key factor to restrict the level of design. It has the thorectical and pratical importanceto find a new, suitable, higher efficient, reusable, easy maintenance verification method.Under this strong demand, VMM arises at the historic moment. This paper makes adeep reseach on this new verification methodology. First, it summarizes VMM in sixmajor characteristics: SystemVerilog language verification, constrained-randomstimulus verification, coverage-driver verification, layered testbench using transactorsverification, assertion verification and reusablility verification. Second, it introduces thestandard library of VMM. Using the basic classes in the standard library, the verificationenginers only need to extend these to build a verification environment which meets theirrequirement. At last, a verification flow combined with functional coverage andassertion is proposed. Using this flow can build a more automatical, reusable, completeand higher efficienty verification environment.In order to put theory into practice, this paper still build a SWP block levelverification environment based on VMM. First, it analyses SWP work agreement; thenit extracts the test feature function and function points of the DUT; finally, it builds ahierarchically, reusable verification environmet, including assertions which verify thetimming of SWP interface.20testcases and15assert statements are used in the sameverification environment. The analyses of result show us that the usage of VMM canimprove the efficiency and ensure the completement of verification. What’s moreimportant is that the block level verification environment can be reused in sub-system orsystem directly which further shorten the verification cycle and reduce the developmentcosts. |
PDF Full Text Request