Design Of UART System-Level Verification Platform Based On UVM

In recent years, with the increase of the scale and complexity of the integrated circuits, verification is getting more and more difficult. The increase of completeness and efficiency in verification is becoming a key challenge. The language used in traditional verification can never satisfy the current requirement from integrated circuit verification.The main work of this thesis is to study the building of a system-level verification platform for a UART module. This module is integrated in a SOPC chip about information processing. According to system-level verification requirement, this system-level verification platform which is based on the UVM method which includes many efficient techniques, such as factory, sequence, phase, register model and so on is divided into two parts, which are system-level components and UVC of UART. Besides, the system-level components consists of system top, system environment, system configure and so on. In the matter of interaction between software and hardware the system-level verification platform and SOPC chip, interruptions from GPIO and platform are adopted to make platform and chip shake hands. Meanwhile, datum in the system-level verification is stored by the SRAM. In addition, through the analysis of data path of the SOPC system, running process of the system-level verification platform is proved. Three steps are used to prove this system-level verification platform is useful, which are building the UART module’s universal verification components, integrating them to the system-level verification platform and verifying the UART module in system-level. Conclusively, coverage for verification of the UART module is given, which includes code coverage and function coverage.The system-level verification platform and UART module’s universal verification components designed in this thesis has been used in project. And the SOPC chip which UART module is integrated in is at the process of tape-out. Simultaneously, the method of the interaction between software and hardware can efficiently resolve the interaction between verification platform and the SOPC chip, which can be referenced by involved staff who works in verification.