Research On IP Level Verification Methodology Based On An High Level Verification Language

Along with the flying development of SOC(System On a Chip)’s operationcapability and complicated degree for control, the functional verification has alreadybecome the main bottleneck in the whole design process. According to the statistics,verification process has occupied2/3or more proportion in the whole design period,and the number of professional verification engineer needed in the design process isalmost2times than the number of RTL(Register Transfer Level) design engineer. Afterthe completion of design, the verification code composes to80%of the whole code. So,verification has become the most important link of key in the integrated circuit designprocess, and it pierced through the whole design process.How to shorten the verification time and enhance verification efficiency throughsome new verification techniques has become one of the most important questionsconcerned in current IC design realm. For this reason, new verification methodology,language and techniques have been developed to break these limitations. Among all thelanguage, SystemVerilog language has been most widely used and supported byVMM(Verification Methodology Manual), OVM(Open Verification Methodology) andUVM(Universal Verification Methodology). However, since there are no a set ofcomplete function verification method, the integrity of verification also can not beguaranteed with these languages and models.Therefore, to solve the above problem, this paper proposes a RTL level verificationmethod basing SystemVerilog and OVM to achieve guiding verification project. Thisverification method is divided into three stages which includes study phase, excitingphase and ending phase and each stage has detailed guidance. For example, completeand precise specifications requirement, comprehensive test plan, constraint stimulusgeneration randomly, the environment as much as possible to reuse and so on, then itcan ensure verification project be controllable and manageable, efficient and complete.For the theory needs to be bounden with practices, there is an verification projectfor SPI_FLASH controller to describe the verification method which is issued by thisthesis, especially about its work flow, and verify its correctness and efficiency.