Research On Functional Verification And MCU Soft IP Simulation Techniques

The development of IC industry and the continuous improving of IC design methodology are interdetermined. And with automation of IC design development, IC scale becomes larger, and verification becomes more important in the design. This paper emphasizes on functional verification research. These research results are implemented to verify 8-bit RISC, which has been designed by our institute and has been named HGD08R01.This paper takes over kinds of ingredients, such as capability and area and timing of chip. And functional verification of RISC puts in practice from kinds of aspects, such as structure, instruction channels, data path, and implement of circuit. As we known, the establishment of verification plan is the key to verification, which closely connects with verification integrality. And the process of functional verification consists of the implementation of RTL (register transfer level) simulation, gate level simulation and post-layout simulation in the process of design. The dissertation introduces into standards of SOC functional verification of VSIA, which consists of organization of standardization. Based on these, we build up verification platform, and mark out the verification plan of HGD08R01, to simulation its function.Also, I have studied on techniques of functional verification, and studied theoretically verification platform. In the result, this dissertation puts forward the methodology of verification platform of automatic comparison, to shorten design periods and eliminate design bugs.