Research On SDRAM Memory Interface Of Network Processor

In recent years, computer networks users and connection bandwidth increase greatly which lead to the growing demand for processing performance of network processor. Memory wall is a key factor to improve processors performance. SDRAM controller is used to control the multi-processor to access external SDRAM and translate commands from processor into commands that SDRAM can execute.Different from conventional single-core SDRAM controller, the SDRAM controller presented in this paper is mainly for the heterogeneous multi-core processors sharing external SDRAM. The single arbitration algorithm is difficult to meet the system performance requirements. In order to access SDRAM fairly, effectively and timely, a hierarchical priority arbitration mechanism is adpoted, including the fixed priority and TDMA (Time Division Multiplexed Access). Besides, a dynamic arbitration algorithm mechanism is added, which hides SDRAM precharge time to improve the efficiency of SDRAM access by providing odd command queue and even command queue.For large Ethernet frame size and long multi-core processor system bus delay and queuing delay, a block data transfer mechanism based on the instruction control is choosen, which can reduce the reading and writing latency and decrease the delay of system bus and interface essentially. For example, SDRAM controller can improve the reading and writing efficiency by 55% at least in processing the IP packet of 64 bytes. Finally, this paper completes RTL description of the various functional modules.Function simulation and performance simulation results show that the SDRAM controller can complete the SDRAM access for multi-processor and achieve the implementation performance up to 200MHz based on the SMIC 0.18μm CMOS processes.