Research On Programmable Logic Design Method For SOPC

System-On-Programmable-Chip(SOPC)is embedded programmable logic compared with common System-On-a-Chips,by adding reconfigurability,greatly increased flexibility,and is gaining popularity.Because the programmable logic design and its usage on System-On-Programmable-Chip have high reference value and engineering practical value for implementing System-On-Programmable-Chip design and application,the in-depth study of programmable logic for System-On-Programmable-Chip has become urgent needs of the industry.Under this background,according to the specific requirements of SOPC embedded with ARM processor and programmable logic,the design method of programmable logic for System-On-Programmable-Chip is studied relying on research projects undertaken by the authors.This paper studies the basic programmable unit structure of lookup table structure based on SRAM programming unit,and uses a hierarchical routing resource structure.The routing resource structure includes four kinds of resources: local routing,general routing,programmable input/output module routing and clock routing.A programmable input/output module for System-On-Programmable-Chip is designed.The function verification platform of input/output module is built,and the function simulation of input mode and output mode is carried out.This paper studies JTAG programming circuit and programming interface.Four kinds of widely used buses are compared in this paper.The AXI bus interfaces including AXI-GP,AXI-HP and AXI-ACP are adopted.On this basis,the architecture of a System-On-Programmable-Chip with processor and programmable logic is studied.In the conclusion part,the research work is summarized,and the design and test of the verification circuit are described.The test results show that the functions,frequencies,output levels,static power supply current,input leakage currents,ESD and other targets of the circuit fully meet the design requirements.At the end of the paper,I look forward to the next work,that is,process imgration and system verification.