Design Optimization Of Static Random Acess Memory Bitcell And Testchip

With the continuous scaling down, the IC manufacturing process has been extended into deep sub-micron area. And with the advantages such as high addressable process defect detection ability and compatible with standard CMOS, embedded SRAM has played a more and more important role in advanced logic process development. It can help developers to easily realize failure analysis and yield prompt.This paper is aimed to research and realize the methodology of optimizing designing the embedded 6T SRAM bit-cell and test-chip based on the project of developing 90nm logic process.We take top three elements into account when designing the SRAM bit-cell: area, power and static noise margin (SNM). First of all, the cell area reflects the manufacturing ability and process margin. Secondly, to decrease the power consumption, we need tradeoff of the cell area. And thirdly, the SNM value stands for the stability of SRAM.Comparing with the common word line SRAM cell used in 0.13um CMOS process, we finished studying and developed another type of cell which is called split word line for more advanced 90nm CMOS process development. Then we finished designing SRAM bit-cells with different cell ratio and further simulation for SNM using HSPICE tool. On the other hand, we took use of the model-based optical proximity correction (OPC) to correct the distorted patterns such as line width variation, corner rounding and line shortening. Finally, we fixed four types of bit-cells for tape-out, and the area of the smallest one is only 0.99um~2. It can meet the area target of this research project.To verify the manufacturability and robustness, we then designed a series of test structures covered front-end and back-end of line. They include the points of junction leakage, isolation, contact resistance, bridging, continuity, device characterization and so on. We also discussed some typical failure modes of SRAM.In the latest and final wafer acceptance test (WAT), we analyzed some key parameters which show excellent performance of the bit-cells. For examples, the junction leakage keeps only 10pA/um or so, and the SNM can be in range of 210-280 mV. All these values can meet the requirements of the target. In a word, the success of this research project has made a concrete foundation for the 90nm process mass-production.