Design And Verifcation Of Large Integer Multiplier Based On An Innovative Booth Algorithm

With the development of Internet technology,the attack on the Internet system has become increasingly complex,and the skills and knowledge of attack required to drop,and the attack becomes more automated and the damage caused greater,information security problem is becoming more and more prominent.Cryptography technology is an important core technology to ensure information security.Public key cryptography has been widely used,and the asymmetric RSA algorithm involved in public key cryptography has become a hotspot in research.The core operation of the encryption/decryption is repeated for the large number of multipliers,which is the most time consuming and most critical operation unit.The operating parameters will restrict the main performance of the encryption /decryption chip.Therefore,the low latency,the parallel and efficient multiplier is of great practical significance to the efficient implementation of cryptographic chip design.In this paper,the Booth algorithm is improved,the multiplier for the improved algorithm is n-bit extended and its design based on FPGA and we verified the accuracy of the algorithm multiplier through hardware and software simulation verification.The realization of the multiplier is based on the design of shift,coding,cumulative operation,bit width expansion.Therefore,this paper mainly studies the common types of adder,Booth algorithm multiplier design method,4-2 compressor principle and implementation,multiplier structure research and design.In this paper,a series of in-depth research is carried out on the basis of Booth multiplier research.Firstly,a multiplier is designed and implemented based on Booth algorithm,and an innovative Booth algorithm based on FPGA is proposed to simplify the Booth coding complexity and reduce the times of additions,only need to do addition operation once;Secondly,basing on the 8-bit multiplier to achieve extensible design,and proposed an extensible large integer multiplier,and has achieved multiplier of 64-bit design,and it can be applied to the Montgomery algorithm modular multiplication,modular power call the core computing module.Thus,improving the speed of the Cryptography operation,simplifying the Booth algorithm design.Finally,the hardware and software simulation experiments are carried out to verify the content of the research and the innovative design method.The delay of key path and the consumption of hardware resources are compared and analyzed,and the summary and prospect of the design of this paper are given.