Researchand Implementation Of Communication Interface In DSP

Digital signal processor, DSP, is a microprocessor with high performance which can quickly realize a variety of digital signal processing algorithms. Because of its features, such as high performance, rich interface and flexible configuration, it has been widely used in communication, automotive electronics, mass storage, audio and video consumer products and other fields.With the rapid development of DSP technology, serial communication interfaces play an increasingly important role. At present, domestic research about serial interface is generally on a single serial interface such as synchronous or asynchronous serial interface. The synchronous/asynchronous serial interface with both synchronous and asynchronous function is unusual. Synchronous/Asynchronous Serial Interface, SASI, with rich function, highly configuration, good compatibility, is widely used in high performance DSP.This paper, beginning with 32-bit high-performance DSP systems, focus on the design of SASI in DSP system. The article starts with SASI principle from synchronous mode and asynchronous mode, and proposes design requirements according to DSP system environment. Top-down VLSI design method is used in this paper. From the system level, analyze SASI and divide it to small modules. Then design these modules in RTL-level, such as registers unit, clock generation unit, sender, receiver and etc. And propose detailed design and implementation methods. In the design process, according to features of synchronous communication and asynchronous communication, rationally reuse common function logic between the both, the area and the power of SASI has been greatly reduced. In addition, fractional frequency divider has greatly reduced error in baud rate. Also, the paper proposed signal synchronization processing techniques in cross-clock domain and Low-power design strategy realized in the SASI. Then from the module-level, top-level to SOC system-level, simulation and verification for design is persuasive. Finally, in TSMC 65nm advanced process library, the paper proposed logic synthesis and timing verification for the design.The result shows that when the clock frequency is 200MHz, SASI can work stably, and its area is 11,231μm2, and the total power consumption is only 507.9μW. So, the design can meet design requirements very well. The asynchronous transfer rate of SASI is up to 12.5Mb/s, and synchronous transfer rate is up to 25Mb/s. The asynchronous transfer rate increases 3 times than similar design, but synchronous transfer rate is much lower than the high-speed synchronous serial interface. It also shows that the advantage in the function is the cost of reducing the transmission rate.In addition, SASI has wake-up mode, which can support multi-processors communication, and it provides a choice for the communication between DSP and other processors. Currently, the SASI has been successfully applied to the 32-bit DSP with high-performance, and it works stably.