The Robust Communication Interface Techniques Researches In MP-SoC

As more and more IP cores can be integrated in a single chip, the clock signaldistribution has become more difficult in such multi-processor system, especially inNetwork-on-Chip (NoC) system. To resolve this problem, the global asynchronous andlocally synchronous (GALS) design method had been proposed and developedgradually in multi-processor system on chip (mp-SoC) design. The ideal GALS mayintegrate heterogeneous cores which use a combination of both synchronous andasynchronous circuits. Heterogeneous cores which are responsible for differentfunctions and have different frequency domains would operate in its own frequency tominimize the energy cost of the whole chip. Then GALS system, which is concentratedadvantages of both asynchronous circuits and synchronous circuits, become an effectivemethod for large scale integrated circuits design, especially for high speed low powermp-SoC and NoC design. In the GALS systems, the communication interface betweenIP cores are the modules which affect the performance of chip seriously, and it is alsoone of the most important and difficult problems in modern mp-SoC researches.Focused on the hot point, the major contributions of this paper are outlined as follows:1. Based on SMIC0.18μm CMOS technology, many asynchronous circuits units havebeen built with the Cadence simulation circumstance. The quasi-delay insensitive circuitmodules have been implemented by using some popular asynchronous circuit protocols.2. The interface used in mp-SoC and NoC was proposed to resolves the problems ofhigh power consumption induced by clock signal and low reusability of IP cores.Implemented by the circular FIFO with threshold gate, the interface removes thesynchronous clock from sender. Data of different widths can be transferred fromsynchronous sender to asynchronous rapidly with the transmission mode combiningboth serial and parallel communication. Since the distributed framework is utilized, thedata transport channel is separated from the transfer control block, as well as thesynchronizer and write/read pointer. In this way, the different reliability requirementscan be satisfied by the interface during changing the number of synchronizer stages, andvarious asynchronous transport protocols are supported gracefully. While the four phasetwo-rail encoding transfer manner is selected in this paper, the transmission isquasi-delay insensitive and the data integrity is ensured.3. A communication interface, which can transfer data from asynchronous tosynchronous module, has been designed based on FIFO operation protocol and highreusability FIFO architecture proposed. Data with different encoded modes can be transferred fast and quasi-delay insensitively from asynchronous to synchronousthrough the the interface with lower power consumption, and various asynchronoustransfer protocols are supported by data transport path in the interface.4. Based on the cycle FIFO system structure, the communication interface betweenthe different time domains has been designed by selecting handshake protocol which isalways used in asynchronous circuits design. By using the interface, the data can betransmitting from one time domain to the other latency insensitively with thetransmission mode combining both serial and parallel. Meanwhile, the data integrity isensured during the communication by the two-rail encoding transfer manner. Thesimulation results have shown that the interface proposed can satisfy the requirementsof high speed low power, strong robustness in Multiprocessor SoC and NoC.5. An asynchronous circuit protocol has been proposed with the nameinner-handshake bundled data protocol. The inner-handshake bundled data has the goodgene from bundle data, but it is used with less timing assumption than the conventionbundled data. The designer would spend less time on the consistence between transportchannel and control module if they use the proposed protocol. Communicationinterfaces for asynchronous protocol transformation have been implemented by usingthe protocol. Simulation results have verified that interfaces is high speed, low power,strong robustness and good reusability.