Robust ultra-low power subthreshold digital circuit design

Operating CMOS circuits with power supplies below the threshold voltage has been suggested for ultra-low power systems. High fan-in/out circuits, such as those in memories, are prone to failure when operating in subthreshold since noise margins are diminished by reduced transistor on-to-off current ratios ION/IOFF. Design guidelines for robust subthreshold logic circuits are developed in this thesis. An analytical model has been derived to determine circuit fan-in/out limitations and the minimum supply voltage for operation. The model is applied to determine subthreshold circuit robustness as affected by fan-in/out and PVT variations.; A 512 x 13b ultra-low power subthreshold memory is fabricated on a 130-nm bulk CMOS process technology. The fabricated memory is fully functional for read operation with a 190 mV power supply at 28 kHz, and 216 mV for write operation. Single bits are measured to read and write properly with VDD as low as 103 mV and 129 mV, respectively. The memory operates at a 1 MHz clock rate with a 310 mV power supply. This operating point has 1.197 muW power consumption, of which 0.366 muW is due to leakage and 0.831 muW is due to dynamic power dissipation. A number of circuit techniques are presented to overcome the substantially reduced ION/IOFF and the poor drive strength of transistors operating in subthreshold, such as gated feedback memory cell, and hierarchical read and decoder circuits. A self-timed control of the keeper transistors is utilized to mitigate increased variability manifested in subthreshold operation.; The write margin and read stability of subthreshold memory cells corners have been analyzed and a more robust subthreshold memory cell was proposed. A semi-quantative model was used to analyze the subthreshold memory Vmin random distribution. Subthreshold memory has different circuit behaviors for write and read "1/0" operation, therefore, their Vmin in PDFs have different envelops. The determination of Vmin requires a guard band for high yield.; A two-stage pipeline microcontroller has been designed using time borrowing to overcome the significant sensitivity to variations in timing. Simulation results indicate that the proposed subthreshold microcontroller timing critical path is dominated by the program memory. Monte Carlo simulation shows wide timing variations and requiring VDD guardband.