The Research And Design Of A New Four Quadrant Multiplier In Subthreshold CMOS

With the increasing development of integrated circuit technology, the scale of the chip is more and more big, and the processing capacity is more and more strong, however, power has become an evermore important issue in the design of integrated circuits, especially in portable electronic devices, we need smaller volume and weight of the battery, but the longer standby time, so low power circuit design become an important direction of the integrated circuit design.Whether in the communications circuit unit or in mathematics circuit unit, the analog multiplier plays a great role, It is most commonly used in the modulation, demodulation, frequency mixer, phase discriminator and analog computation, thus the design of analog multiplier with low power and high precision has very important significance.In this article, you will see a new structure of the four quadrant analog multiplier, and the new structure bring many benefits to the performance of the multiplier. First, unlike Gilbert multiplier, we adopt current mirror with bulk driven technique to achieve multiplication, this is helpful to wide input linear range. Second, the four quadrant multiply is implemented by vector matrix multiply, this structure is convenient to extend the multiplier. Third, CMOS-process-compatible Quasi-floating gate MOSFET can decay input signal and fix DC bias. Fourth, the multiplier works in subthreshold with low supply voltage, so its power consumption is very low. Fifth, the voltage mode module is easy to integrate in circuit, while the current multiplier has a higher bandwidth.The multiplier in this thesis is designed and simulated in Cadence5.10.41 using standard model parameters for TSMC 0.18 um fabrication process, the supply voltage is 1V, the total current is less than 100 n A, the power consumption is no more than 0.1 ?W, its input voltage linear range is 300 m V, the non-linear error is less than 3%, the total harmonic distortion is less than 1.05% the-3d B bandwidth is 1.3MHz when bias current is 30 n A. In comparison with Gilbert multiplier, the multiplier has bigger bandwidth, wider input linear range, smaller area and so on, thus, which has greater potential in low power analog circuit.