Design Of A 27M CMOS Frequency Synthesizer With Phase-locked Loop Technology

The frequency synthesizer is a key component in wireless communication systems currently, whose performance has a direct impact on the communicated quality of entire system. Thanks to the wider frequency capyure range, lower locked phase error, lower power consumption and lower cost, charge pump phased-locked loop technology has been widely used in frequency synthesizer.Firstly, the operation principle, mathematical medel, transient characteristics, stable condition and the noise transfer function of change pump PLL is analyzed, and loop bandwith optimization and selection is also discussed, with an emphasis on system point. Followedly, the design consideration of the charge pump PLL frequency synthesizer building blocks is dicussed by detailed, and the performance of the common circute structure is compared. Finally, with the tradeoff between such requirements as power consumption, cost and noise, it design a charge pump PLL frequency synthesizer with output is 27M, used in amateur radio channels. The frequency synthesizer integrated all components on a single chip. It mainly includes crystal oscillator, PFD, charge pump, loop filter, VCO, divider and so on. Meanwhile, it also design three LDO blocks in order to reduce the power supply noise.0.5um CMOS mixed signal technology of CSMC is used for designing the circuit. The layout is drawn by the tool of virtuoso, which is offered by Cadence Company. Then do the DRC, LVS checking, parastic extraction and post-simulation. The overall chip area is 850um×1000um. Simulation result shows the LDO needs 20uS to establish a stable output voltage, crystal needs 2.3mS to establish a stable oscillation. PLL will be locked after 45uS if the output of crystal oscillator is stable.