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Low Power And Testability Design And Static Timing Analysis For Small-Medium LCD Controller

Posted on:2005-02-02Degree:MasterType:Thesis
Country:ChinaCandidate:H YangFull Text:PDF
GTID:2168360152467609Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
LCD controller is a Graphic/Image displaying control chip for LCD applications, the main function of the LCD controller is simple Graphic/Image processing before providing synchronous signal and displaying data to the LCD panel. For recent years, the LCD controller becomes more and more popular and complicated as the great demand of communication and mobile products increase.The LCD controller discussed in this thesis is applied for small/medium scale LCD graphic displaying control. Low power and testability are mainly discussed in this thesis, and a full low power design scheme and test methodology is proposed for the chip. Multiple popular low power technologies such as Dynamic Power Management, memory partition, pre-computing, etc are used in different design level. The power is remarkably reduced with a small cost of area. And the LCD controller provides good support to the system low power application since there are multiple internal clocks in the chip and the clocks' frequency can be re-configured in working state. Also it can be configured in power save mode. Scan testing for core logic and MBIST circuits for embedded memory are adopted for testing. With a very small extra number of circuits, the testability problem was removed which is caused by the asynchronous clocks and embedded memories. There are total 16 scan chains in the chip, and the test pattern was generated in Synopsys TetraMAX. High test coverage is achieved through ATPG faults simulation.Low power requirement is taken into account for the LCD controller testability. In scan test state, memory clock is shut off and memory read/write operation is forbidden. In MBIST test mode, the clock of core logic and MBIST circuits that don't work is shut off. As a result, unnecessary power consumption is saved.The last part of this thesis gives the results of pre-layout and post-layout Static Timing Analysis. It proves that no timing problem exists in the LCD controller.
Keywords/Search Tags:LCD controller, low power, testability, scan test, ATPG, MBIST, test coverage, Static Timing Analysis
PDF Full Text Request
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