Design And Implementation Of Pipeline RISC CPU Based On FPGA

Along with the quick development of micro-electronics technical, the integrationdegree of integrated circuit is more and more high.This trend pushes the embeddedsystem from the ages of traditional system on a board into the ages of system on achip. However the CPU is the core of SoC, it is the key research problem that how toDesign and implement valid CPU.Based on modern EDA technique, A MIPS style five stages pipeline RISC CPUwas designed and implemented on FPGA. During the design and implement of CPU,there is main research as follows:(1)MIPS architecture was selected as the frame of CPU. According to MIPS in-struction set, the instruction set of CPU was designed. By abstracting the commonnessof each instruction in the instruction set, the five stages (IF, ID, EXE, MEM, WB)pipeline data path was designed with pipeline technique. Functional module on thedata path was implemented with VHDL.(2) According to the control signal needed by data path, the control path wasdesigned to make the data path work e?ectively. Aim at control hazard, a module wasdesigned for detecting hazard. The interrupter was designed for solving abnormity andinterrupt. The control path, detecting module and interrupter were implemented withVHDL.(3) Based on FIFO and LRU algorithm, two kinds of instruction Caches weredesigned for the characteristic of the CPU. The two kinds of Caches were implementedwith VHDL. Finally the two algorithms on the two Caches were simulated and analysed.(4)For difference function of the CPU, test procedures were writed with the instruc-tion set, and test procedures were run for simulation. It was found that the verificationwas consistent with the simulation when the electric circuit document was downloadedto hardware terrace and run off. The result shows that the CPU is effective.