Design And Research Of 5-stage Pipeline Processor Based On RISC-V

From ultra-low-power microcontrollers to big data high-performance computing,to artificial intelligence heterogeneous computing,CPUs all play a core role.Different application scenarios have different requirements for CPU performance.At present,the complexity of the instruction set based on the x86 processor architecture,the high investment cost,and the difficulty of research and development make it gradually no longer advantageous in the embedded field.Although processors based on the ARM instruction set architecture occupy a large market share of embedded processors,they are not the core of domestic microprocessors.The authorization is restricted by foreign companies.Under the strategic requirements of domestic substitution,domestic microprocessors are urgently needed.Make substitutions.The open instruction set RISC-V microprocessor is precisely because of its advantages of low power consumption,low development difficulty,independent research and development,etc.,it has gradually been recognized and valued in the development of embedded microprocessors.The design of this thesis is mainly based on the research of RISC-V instruction set architecture,E203 processor and HBird-E200-SoC,and proposes a five-stage pipelined processor core design based on RISC-V architecture.On the basis of completing the processor core design,taking Freedom-E310 SoC as a reference,making full use of and modifying the existing IP for peripheral modules such as UART,SPI,GPIO,and I2C,and completing the five-stage pipeline processing based on RISC-V Finally,a simulation test platform was built to simulate and test the designed processor core and peripheral modules,and the constructed SoC was prototyped with FPGA for verification.First of all,for the pipeline design of the processor core,a classic 5-stage pipeline architecture is adopted to improve the utilization of each pipeline and solve the data hazard problem generated by the pipeline and the suspension caused by the memory access operation,which causes performance degradation.In the "fetch" unit design,the instruction register adopts the instruction coupling register design to ensure "fast"instruction fetching.At the same time,the branch prediction design is adopted to effectively avoid the performance loss caused by the flushing of the pipeline caused by the conditional jump instruction;The "execution" unit has designed a bypass circuit module for the correlation between WAW and RAW data in the pipeline;the "fetching"unit design adds a memory access control signal to determine whether it needs to be suspended,thereby improving the utilization and throughput of the hardware module rate.The simulation test platform first performed a simulation test on the processor core,wrote an assembly test program according to the instructions in the instruction set architecture,and performed a functional test on the processor core;then,it simulated each peripheral module in the SoC,according to different peripherals.Write different test codes to complete the simulation and testing of each peripheral module to ensure the integrity of its functions;finally,based on the Xilinx ARTY A7 FPGA development board,the designed SoC is prototyped with Vivado tools for verification.