Design Of PFD And CP Based On 0.18um CMOS Processon

Application Specific Integrated Circuit(ASIC)can greatly reduce the overall cost,improve the reliability,confidentiality and competitiveness of the system,reduce power consumption,increase the speed of system operation,etc.In an ASIC chip,the clock generation unit as a module to generate and control the clock is a very important analog components.In order to ensure performance of system and current trend,the clock generation unit generally requires a low jitter and higher frequency characteristics,usually with a phase-locked loop(PLL)as the clock generation unit.Phase frequency detector(PFD)is one important modules in Charge Pump PLL(CPPLL),and charge pump(CP)is another one.In this thesis,the research and design of the CPPLL sub-module PFD and CP circuits use 0.18μm CMOS process,and make further improvements and innovations in the circuits based on theoretical analysis.To reduces the delay dependence of the reset signal on the D flip-flop(DFF)in the PFD module,this paper proposes a new PFD circuit structure.Compared with the reset signal generated by the DFF and the AND gate,the reset signal of the circuit designed this time depends on input signal delay and output of the DFF.This structure increases the phase detection range,eliminates dead zone,and reduces blind zone.The source-switched single-ended output CP circuit with an operational amplifier is devised to improve matching performance of charge pump and increase output voltage range when matching the charge and discharge currents by using the "virtual short" principle of the operational amplifier for level clamping,and reduces the imperfect effect of CP circuit.After completing design of the circuit diagram,the circuit was verified by pre-simulation and the layout was devised in line with circuit diagram.Verify Post-simulation of the designed layout: the performance of the designed PFD&CP is good and meets index requirements,at three different process angles of tt,ff and ss,the logic level of the PFD module is correct,no dead zone,phase detection range is bigger than(-1.976π,1.976π),when the output voltage of the CP module is within0.144～1.476 V,the charge/discharge current is changes in tne range of 57.84～58.32μA,the charge/discharge current mismatch is less than 0.4899%.The maximum power consumption of PFD&CP at the same frequency and phase is 291.59μw.Based on Verilog-A language and ideal components,LPF,VCO and FD are modeled at behavioral rank,together with PFD and CP module designed in this paper,a third-order CPPLL is formed.Simulation shows the time-domain locking time of CPPLL system is less than 17.99μs under three different process angles tt,ss,and ff.