Research On Key Circuits Of High Performance Pipelined ADC

As the electronic technologies move forward in the society, the conversion between analog signals and digital signals plays a very important role in the whole signal processing. Acting as the bridge between analog and digital world, Analog-to-Digital Converters are widely used in many areas, including the wireless RF local network, image technology as well as all kinds of sensors. Among all kinds of ADCs, pipeline structure could make a better trade-off between speed and resolution. For a high performance pipeline ADC, its key circuits'features are of great importance to the all system. Clock signal's duty cycle, driving ability and jitter are the key facts that influence the resolution. Meanwhile, as the basic units of quantization in every sub-ADCs, the speed and accuracy of comparator limit the corresponding characteristics of whole ADC.This thesis proposes high speed clock stabilizer and low power high speed comparator used in high performance pipeline ADC based on TSMC 0.18μm 1P6M CMOS process. Both chips have been taped out, and the test results are qualified. High speed clock stabilizer can stabilize an input clock with 10 to 125MHz frequency and 10%-90% duty cycle to 50% duty cycle with only±0.5% error. Low power high speed comparator can operate under 100MHz frequency with less than 2ns responding time and 30mV offset voltage, its dynamic power consumption is only 0.264mW.Firstly, the thesis would recall the development of clock circuits and comparators in recent years and analyze the principle of pipeline ADC along with its key circuits, giving the influence that core units could make. In chapter 3 and 4, the proposed high speed clock circuits and low power high speed comparator would be discussed in detail. Chapter 5 introduces the layout and test of both chips.