| MOS Current-Mode Logic (MCML) is a low-noise alternative to CMOS logic for mixed-signal applications. If properly designed, MCML circuits can achieve significant power reduction compared to their CMOS counterparts at frequencies as low as 300MHz. MCML logic has, however, fallen out of favor because of its high design complexity and the lack of automated design and optimization tools.; In this work, simple and accurate propagation-delay models for MCML circuits, that are suitable for mathematical programming, have been developed and verified. The models are based on a modified version of the differential-pair MCML universal gate. The modified universal-gate performance has been compared to the standard universal gate topology. Simulations have shown that the modified universal gate has better DC symmetry, lower switching noise and higher operation frequency.; When compared to simulation results, the proposed delay model has an average error of about 3.7% and a maximum error of 12%. The proposed model has significantly reduced the complexity of the MCML universal-gate optimization problem. When compared to the most recent work, the proposed model has reduced the number of optimization variables from 7N+1 to N+1, where N is the number of logic gates in the optimization problem. The optimization problem constraints have also been reduced from 5N to only one constraint. The model has been successfully implemented to optimize a 4-bit ripple-carry adder and an 8-bit decoder. Numerical tests show that the proposed optimization program produces the global solution regardless of the initial guess. |
