Research On Low Power And Glitch-resistant Double Edge-triggered Flip-flop

With the rapid development of integrated circuits,the process size of integrated circuits is shrinking,the number of transistors integrated in integrated circuits is also increasing sharply,and the required clock frequency is also greatly increased,which is accompanied by rapid growth of power consumption.In recent years,with the development of electronic wear technology,the miniaturization,integration,and low power consumption requirements of integrated circuits have become higher and higher.As a basic component of digital integrated circuits,flip-flops are widely used in large-scale digital integrated circuits.Related studies have shown that the clock power consumption of sequential circuits accounts for a large proportion of the total power consumption of digital integrated circuits.In synchronous digital VLSI design,the clock system is mainly composed of a clock tree circuit and a sequential circuit.Therefore,the research of low-power flip-flops plays a very important role in the design of low-power large-scale digital integrated circuits.There are many factors affecting the power consumption of the CMOS circuit,including the size of the power supply voltage,the clock signal frequency,the size of the circuit node capacitance,and the activity factor of the circuit.There are many ways to implement digital integrated circuit low-power technology,including clock gating technology,lowering the power supply voltage,using smaller integrated circuit process sizes,and reducing redundancy jump of circuit and so on.The clock gating technology mainly reduces the power consumption of the circuit by controlling the turn-off of the inactive part of the circuit at a certain moment.The power supply voltage is related to the specific process size.Once the process size adopted by the integrated circuit is determined,the power supply voltage is determined.It can't be changed at will.Another way to effectively reduce the power consumption of the circuit is to reduce the redundancy jump in the circuit as much as possible.Due to glitch exist widely in digital circuit systems,this dissertation proposes a low-power double edge-triggered flip-flop that can resist glitch.The overall idea is to use C-element to successfully block the input glitch of the circuit and reduce the redundancy in the circuit.The transition reduces the overall power consumption of the circuit,and on the other hand implements the function of the double edge trigger.The advantage of a double edge-triggered flip-flop over a single edge-triggered flip-flop is that at the same clock frequency,the data throughput of the double edge-triggered flip-flop is twice that of a single edge-triggered flip-flop.A flip-flop that implements a double edge-triggered function is more complex in circuit structure than a single edge-triggered flip-flop,and uses more transistors than a single edge-triggered flip-flop.This requires weighing the area overhead of the circuit and the power consumption of the circuit.In this dissertation,the product of power consumption,delay and circuit area is used to compare the performance of the circuit,which is relatively fair to a certain extent.In this dissertation,the proposed circuit structure and the circuit structure proposed by the predecessors are fully simulated by using HSPICE software.A large number of simulation experiments show that the proposed double edge trigger can effectively shield the impact of the glitch on the circuit.The device has achieved a good compromise between power consumption,delay,and area overhead.Compared with the other five kinds of double edge-triggered flip-flops,the total power consumption of the double edge-triggered flip-flop is reduced by 40.87%~72.60%.The total power consumption with glitch is reduced by 70.1% ~ 70.2% on average,only increasing the average area overhead of 22.9% and the average delay overhead of 5.9%~6.8%.