Besign Of Low-power Flio-flops Based On65nm CMOS Process

With the continuous development of CMOS integrated circuits, the integration is increasing, the clock frequency become more and more high, and the power consumption is dramatically increased with them. Excessive power dissipation of integrated circuits put forward higher requirements of the thermal performance and stability of the equipment, and the endurance of a variety of mobile portable devices is also under increasing challenge. Therefore, low-power design is increasingly important in the VLSI design process. On the other hand, as device dimensions continuing to shrink, MOS transistor no longer performs as an ideal voltage controlled switch. Increasing integration makes the interconnection account for a growing proportion of the circuit, the signal integrity and power consumption problem brought by interconnection are becoming worse. The usage of multi-valued logic or negative resistance device to reduce the number of devices used to achieve the same functional circuit is an effective method to solve the problem. Due to its unique current-voltage characteristics, negative resistance device can greatly enhance the logic function it can achieve, which helps to reduce the number of devices used to achieve the same function. Negative resistance device is receiving more and more attention.In the VLSI circuits, the power consumption of the clock system accounted for almost one-third of the total power consumption. In the clock system, the power comsumed by flip-flops and the buffers that directly drive them account for about90%of the power consumption of clock system. Therefore, the design of low-power flip-flop has a very important significance on reducing the power consumption of the whole chip.Compared to the master-slave flip-flop, pulse-triggered flip-flops have simpler structure. They usually make up of only one latch and have a very big advantage in terms of power and speed. In addition, the design of flip-flop based on the CMOS negative resistance device is very few. So, this thesis is mainly about the design of low-power pulse-triggered flip-flop design and flip-flop design based on CMOS negative resistance devices. Firstly, a single edge pulse-triggered flip-flop CCFF based on conditional clock technique is proposed, CCFF has obvious advantage in terms of power consumption when the switching activity of input data is low. Conditional clock technique combines the advantages of clock edge trigger control and clock gating technique, so CCFF can block the clock singal when the data input and output signal remains the same, which will suppress unnecessary pulses and reduce redundant transitions of its internal nodes. Therefore the power consumption of CCFF is greatly reduced. Secondly, a single-edge pulse-triggered level converting flip-flop CC-LCFF based on conditional clock technique is proposed, CC-LCFF has very low power consumption and is very stable. CC-LCFF can block the clock singal when the data input and output signal remains the same, so its pulse generator can not generate the delay inverted signal of clock, which will suppress redundant triggering of the flip-flop and reduce redundant transitions of internal node, thereby greatly reduce power consumption. Finally, based on analysis of the characteristics of negative resistance device and MOBILE (MOno-stable B1-stable transition Logic Element), a clock rising edge triggered D flip-flop using CMOS MOS-NDR negative resistance device is proposed.Based on SM1C65nm CMOS technology, Hspice(?) post-layout simulation results show that the proposed novel CCFF has obvious advantages in terms of power when the data input switching activity is10%, the reduction of power consumption is about42%to71%as compared with homogeneous flip-flops proposed in other literatures and the variation of its performance under different PVT conditions and process corners is small. However, CCFF’s delay is larger due to the conditional clock technique, so it’s suitable for using in non-critical paths that require low-power consumption. As compared with homogeneous level-converting flip-flops proposed in other literatures, the proposed novel CC-LCFF has the lowest power consumption when the switching activity of data input is below80%. When the switching activity is10%, the reduction of power consumption is about66%to73%. Moreover, the variation of CC-LCFF"s performance under different PVT conditions and process corners is small. So, CC-LCFF is very suitable for using in low power CVS systems with dual supply. The proposed novel D flip-flop based on CMOS MOS-NDR negative resistance device has correct logic function. As compared to the other D flip-flop design based on MOS-NDR, the newly proposed D flip-flop shows much robust output and stronger anti-interference ability.