Research And Design Of Low-Power MCU System

With the rapid development of IC design technology, the scale of chips and the integration of chips, the influence of power consumption on circuit have become the factor IC designer must first take into consideration. Some researches show that the power consumption of IC has increased tremendously with the sharp advance of integrated circuit fabrication technology. The increasing of power consumption not only wastes resources, but also bring about a series of problems, for example, chips failure effects, environmental influences environment, the increased costs of chip manufacturing. So, reducing IC power consumption is imperative.In digital integrated circuits, the most common elements are latch and flip-flop. They are not only the starting and ending points of signal delay paths, but also indispensable components of every sequential system. The power analysis of a high-performance processor shows that a large part of the clock power consumption is used to drive sequential elements. Therefore, reducing the power consumption of latches and flip-flops, especially clock distribution network, are important for reducing total power consumption of chip.The main works and creative methods are as follows:First, this thesis makes emphasis on the sources of power dissipation in a CMOS circuit, meanwhile some technologies and methods of reducing the power consumption in the design levels of process-level, layout-level, gate-level, register-transfer-level, system-level and circuit-level are given.Second, analyzing the work principle of the energy recovery technology and its realization. Moreover, under the guidance of energy recovery technology and inspired by the traditional structure, the thesis proposes single-edge triggered static differential flip-flop (SETSDFF). SETSDFF has the following advantages. The structure of static CMOS latch complementary way, makes the circuit have good performance and 0 static power consumption etc. Dynamic clock circuit design can not only reduce the circuit's dynamic power, but also improve the speed of the circuit. The approach of dual-rail input data, help to reduce the response time of the circuit and improve system speed.Third, on the basis of proposed SETSDFF, this thesis also proposes double-edge triggered static differential flip-flop (DETSDFF), and has a detailed comparison of the power, time characteristics and layout area of single and double-edge trigger flip-flop.In the SMIC 0.35um CMOS standard process, 3.3V, and 27OC, circuits are simulated by use of Spectre software. The results show that in the case of 40MHZ, 50% data conversion behavior, the SETSDFF controlled by square wave clock consumes energy 133.7uJ, and the SETSDFF controlled by sine wave clock consumes energy only 76.4uJ. At 200MHZ, 100% data conversion behavior, the power of DETSDFF consumes 310.6 uW.Last, a conclusion of the thesis is presented, and some further prospects of the research are made.