Research On Key Techniques Of Low Power Double Edge Triggered Flip-flop Design With Blocking Glitches

The rapid development of the integrated circuit industry,on the one hand,is making the power consumption problem of integrated circuits and chips increasingly serious.On the other hand,plenty number of applications about portable electronic devices represented by smart phones and tablets,as well as the rapid increase in integration and operating frequency,have significantly increased the power consumption of their circuit systems.Therefore,low-power design technology occupies an increasingly large part in the design of VLSI circuits.As an important part of sequential circuits,flip-flops are widely distributed in digital integrated circuit systems.The design of low-power and high-performance flip-flops is particularly important.For CMOS integrated circuits,there are many factors that affect its power consumption,including operating voltage,clock frequency,signal switching activity,and so on.For these aspects,there are corresponding low-power design technologies to reduce the power consumption of CMOS circuits,such as the use of more advanced integrated circuit manufacturing processes to reduce the operating voltage and node capacitance;clock gating technology is used to temporarily shut down non-working transistors and circuits to reduce the switching frequency of internal nodes,etc.In the working process of digital integrated circuits,the indispensable ones will be affected by glitches.The interference of the external environment,the competition and risk generated by the upper-level combinational logic,etc.will cause much glitches on the input signal of the flip-flop.These glitches are transmitted to the inside of the flip-flop,which inevitably brings about the charging and discharging of additional internal nodes,making its power consumption increased significantly.In response to the above problems,this dissertation proposed a low-power double-edge triggered flip-flop design which can block glitches.The C-element is used as the basic component to redesign the internal latch of the double edge triggered flip-flop,which effectively blocks the glitch in the input signal.Inside the device,the redundant transitions are reduced,and the power consumption of the flip-flop is significantly reduced.Compared with a single-edge triggered flip-flop,a double-edge triggered flip-flop performs sampling on every edges of the clock,and only needs half of the clock frequency to achieve the same function,which can effectively reduce the clock tree's power consumption.Based on the PTM 32 nm model,this dissertation used HSPICE software to simulate the double-edge triggered flip-flop and the related comparison structures.Extensive simulation experiments show that the double-edge triggered flip-flop proposed in this dissertation can effectively block the glitch,reduce its impact on the circuit and additional power consumption,and achieve good overall performance in terms of power consumption,delay,area,other indicators.Compared with the related ten kinds of double-edge triggered flip-flops,the total power consumption of the double-edge triggered flip-flop circuit proposed in this dissertation is reduced by251.17% on average,the delay is reduced by 9.71% on average,and the power delay product is improved by 44.32% on average.When the signal has glitches and the number of glitches is small and large,the circuit power consumption is reduced by43.62% and 51.28% on average.The detailed analysis of process,voltage,temperature,aging variations shows that the double-edge triggered flip-flop is not sensitive to PVTA variations.