| High-speed interface circuits play an important role in bridging the outside and inside of the chip and attaking their different frequencies. With the development of the information technology and integrated circuits, integrated circuits system becomes more and more complex, the amount of data increased quickly, the demands on the I/O interface improved seriously. I/O interface becomes a bottleneck in high-performance systems.CML (Current Mode Logic) is another low-voltage differential signal transmission technology of high-speed data transfer interfaces after ECL, LVDS. CML, widely used in the network physical layer and high-speed SerDes circuit, has the advantages of high-speed, low noise and low power consumption, etc. It is a new technology solution to the I/O interface issues. Based on the standards of ANSI/TIA/EIA-644, the thesis focuses on the CML sending circuits. And the high-speed converter circuit of"parallel to serial"and CML transmitter module are analyzed thoroughly and designed.In order to meet the requirements of high speed in"parallel to serial"conversion circuit and combined with the advantages of tree and parallel structure, a 10:1"parallel to serial"conversion circuit comprisd of two low-speed 5:1"parallel to serial"converters and a high speed 2:1"parallel to serial"converter is designed. The tree structures effectively reduce the overall circuit power consumption and the design complexity. The designed parallel structure uses a series of C2MOS D flip-flops to adjust the phase relationship between the clock and data, gain a greater phase margin compared to the ordinary parallel structure and therefore improve the reliability of circuit. The combination of the tree and parallel structure not only meets the stringent demand in"serial to parallel"conversion, but also redue the working frequency in most parts, the power consumption, the data jitter. The results of Hspice simulation show that, the root mean square of random jitter (RMSjitter) in serial data output under TT case is 0.68585% of the clock cycle; the core circuit power consumption is 1.68mW, less than the same circuit.In the CML transmitter circuit, the level conversion circuit, single-ended differential switching circuit and pre-emphasis circuit is designed. The level conversion circuit uses a improved structure, and therefore, the output has a high swing level, good stability, a duty ratio of 50%. A single-ended differential switching circuit with clock control is proposed, which has symmetry differential output waveform and good stability of common-mode level remains at 500mV. A current-mode pre-emphasis circuit with the precise controlled delay is proposed by parallelly connecting many small current sources. This circuit can also implement the pre-emphasis amplitude adjustment by controlling the tail current. In 5Gbps data rate circuit simulation, results show that the emphasis of the first circuit level increases about 10% and the primary part increases about 20% significantly. Results also show that the signal swing at the differential output of CML transmitter is close to 800mV, the signal swing at the load end of the differential signal transmission line is 300mV.Finally, the thesis studies the analog-digital mixed layout design methodology, and discusses crosstalk, noise, matching, antenna effect, latch-up and parasitic effects in detail, and gives the corresponding solutions. Based on the CMOS process of 1P8M 65nm, the circuit layout design is completed with the design approach combined with full-custom and semi-custom. |
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