Design And Implementation Of High-speed Communication Method Based On Serial Channel

In the era of big data, huge data sets are growing explosively. Massive data streams are posing greater challenges to data processing abilities of modern communication systems and data communication bandwidth. Conventional parallel transmission method faces a bottleneck to further improve the data transmission rate. The serial link system primarily used for fiber optic communication in the past are gradually replacing traditional parallel link system and becoming the mainstream of high speed data interface technology. And low voltage differential signaling technology (LVDS) has been widely applied at many high-speed serial occasions.In this paper, based on an in-depth analysis and study of the high-speed serial bus communication theory and related knowledge, the high-speed differential serial bus transmission channel is designed and implemented on FPGA. Therein, the key modules of the serial channel transceiver are designed, including8B/10B encoder,8B/10B decoder, serializer, de-serializer, CRC check module, differential signal transceiver, etc. Then simulation and verification are performed on each module to ensure the function correctness of each module. The utilization of8B/10B encoding technology adds2bit redundancy symbols to the raw data, but increases the signal integrity of transmission channel; the use of8B/10B decoding technology can detect error code, ensuring reliability of the channel. At the same time of improving data transfer rate, to improve system bandwidth, multiplexing technology is adopted based on one-way serial channel to form a multi-channel array of high-speed communication.A high-speed transmission approach--differential write-only bus (DWOB) is presented in this study, which designs the unified node access protocol of DWOB and defines the frame format of message packet on DWOB. DWOB bus and a master processor node (MPN) and some slave processor nodes (SPN) together form a topology, making all node interfaces unified to facilitate scalability, and message interaction between nodes is completed with message transmission.Based on high-speed differential serial channel, a novel differential DDR SDRAM memory architecture DSDDR is proposed by applying it to data storage system. In the design, the control commands, address, data and so forth sent by the host in parallel are encapsulated into message packets and sent to the DDR memory via high-speed differential channels, completing the data read and write operations. Meanwhile, a DSDDR memory array is also designed. Through simulation and verification on FPGA, the system is of excellent stability and reliability.