Design And Research Of High Speed LVDS Driver

With the development of integrated circuit manufacturing and design technology,as well as the arrival of 5G era of communication,the demand for high-speed signal transmission interconnection is increasing day by day,which puts forward higher and higher requirements for the speed and quality of data transmission of transmission interface circuit.At present,the domestic existing TTL,RS-422,RS-485,SCSI and other transmission standards are limited by many complex factors such as speed,noise,power consumption and cost,which can not meet the various requirements of today's high-speed data transmission.The emergence of LVDS technology solves these problems.Low voltage differential signal(LVDS)technology uses a very low voltage swing of 350 m V to transmit data signals on a pair of differential transmission lines.It can make the data signal transmission rate reach several hundred Mbps,and has strong anti noise ability,low power consumption and low manufacturing cost.It is an effective technical way to realize highspeed and high-quality data signal transmission.Based on the LVDS ANSI/TIA/EIA-644 A standard,this thesis studies the high-speed LVDS driver circuit in LVDS interface,and summarizes two problems that hinder the speed increase of LVDS driver: the dynamic offset of output common mode level and the loss of high frequency components in transmission.The dynamic offset of common mode level leads to the offset of output LVDS signal waveform,and the loss of high frequency component leads to inter code interference and increase of error rate.These two problems will seriously reduce the quality of output LVDS signal and hinder the speed of LVDS driver.The solution is proposed to solve these two problems,and the common mode feedback circuit and the pre-emphasis circuit are designed.The overall circuit of high-speed LVDS driver designed in this paper includes single ended to differential circuit,common mode feedback circuit,pre-emphasis circuit and main driver circuit.The common mode feedback circuit can monitor and adjust the output common mode level in real time in the process of data signal transmission,so as to maintain it at a stable value;the pre-emphasis circuit can compensate the high-frequency component of the data signal in the process of transmission,so that the output LVDS signal contains more highorder harmonic components,which is closer to the rectangular wave and eliminates the inter symbol interference,The bit error rate is reduced and the quality of LVDS signal is improved.In this design,the main driver circuit uses three current sources in parallel to supply power to the main driver circuit,including the main drive current source,common mode feedback current source and pre-emphasis current source,which realizes the high speed and stable conversion of CMOS signal into LVDS signal.Based on 0.11?m CMOS process and using Cadence Virtuoso tool,the circuit structure of the high-speed LVDS driver is simulated and verified.The results show that the transmission rate can reach 1Gbps,the output common mode level is maintained at 1.25 V,the common mode offset is less than 0.15 V,the output LVDS signal swing is 350 m V,the eye opening is90%,the 7p F capacitive load can be driven,and the static power consumption is less than12 m W,which achieves the expected design target.