Design Of A 14 Bit 100ms/s Pipeline ADC

With the development of digital signal process technique, wireless communication technique get unprecedented development. High performance ADC (Analog-to-Digital Converter) is needed in wireless communication technique. This paper is focus on pipeline ADC which is widely used in communication system.This paper firstly introduce the architecture of pipeline ADC system, it contains pipeline ADC's performance parameters and all the non-ideal parameter in pipeline ADC. Then this paper analysis all the circuit of pipeline ADC, it contains OTA (Operation-Transconductance-Amplifier) circuit, comparator circuit and Bootstrap switch. Simulation results show that when the capacitors have no mismatch, SNDR(Signal to Noise and Distortion Ratio)is 77.65dB,and SFDR(Spurious Free Dynamic Range)is 90.71dB. While if capacitors'mismatch is 0.1%, SNDR(Signal to Noise and Distortion Ratio)is 66.77dB,and SFDR(Spurious Free Dynamic Range) is 76.22dB。This paper then introduces digital calibration technique in pipeline ADC. It contains two different digital calibration technique, one is LMS (Least Mean Square) adaptive algorithm background digital calibration. The other is PN (Pseudo Noise) Dithering based digital calibration. Model is established in MATLAB, and simulation results show that the ENOB (Effective Number of Bits) can improves from about 8 bits to above 12 bits.