The Rreasch And Design On Q-DDFS System

In this thesis, introduction and summarization of the direct digital frequency synthesizer (DDFS) are carried out. Its fast frequency switching, fine frequency steps and good spectral purity have made it popular in a myriad of applications in communication systems. The thesis introduces four kinds of the common DDFS synthesis method and four kinds of synthesis methods are compared between the advantages and disadvantages. Based on the power and the spectrum purity, the synthesis methods are analyzed. Compared to other methods, the quadratic polynomial approximation algorithm has comprehensive advantages over power and spectral purity.To design a Q-DDFS which requires less hardware and works at a higher operating frequency, this thesis presents a design of Q-DDFS with phase-to-sinusoid amplitude converter based on the improved the quadratic polynomial approximation algorithm—a decomposition algorithm of the quadratic polynomial approximation. A detailed and systematic procedure for the selection of quadratic segment coefficients is proposed from the analysis of both logic elements and spectrum. A Q-DDFS architecture based on FPGA with the character of less logic elements is implemented by selecting appropriate coefficients. This ROM-less and no complicated logic circuits is totally composed of digital circuits, and is very suitable for mixed signal circuits and communication systems which demand low power consumption and high integration level.A Q-DDFS based on sixteen segmented decomposition algorithm is implemented, this design could work at 147MHz and achieves 110.9dBc of SFDR and 0.03Hz resolution. Then system delay is eight clocks about 54ns. This circuit is implemented with Verilog HDL and is simulated and synthesized with QuartusⅡ, then the system output is analysed with Matlab between the time domain and frequency domain. The simulation results show that the proposed Q-DDFS circuits is 20% less than the conventional approximation in logic elements and increases the maximum operating frequency by 24MHz and 10MHz of bandwidth. It is shown that the synthesizer based on this algorithm, in terms of logic element consumption and operating frequency, is significantly advantageous than that of the quadratic polynomial approximation algorithm designs. Compared with other methods, the decomposition algorithm of the quadratic polynomial approximation also has superiority over SFDR and frequency resolution.